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Integrated Circuit Systems, Inc.
ICS950211
Programmable Timing Control HubTM for P4TM
Recommended Application: Brookdale and Brookdale -G chipset with P4 processor. Output Features: * 3 - Pairs of differential CPU clocks (differential current mode) * 5 - 3V66 @ 3.3V * 10 - PCI @ 3.3V * 2 - 48MHz @ 3.3V fixed * 1 - REF @ 3.3V, 14.318MHz * 1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps
Pin Configuration
VDDREF X1 X2 GND 1 PCICLK_F0 1 PCICLK_F1 PCICLK_F2 VDDPCI GND 1 *WDEN/PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 *PD# VDDA GND *Vtt_PWRGD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF FS1 FS0 CPU_STOP#* CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTSEL0* I REF GND FS2 48MHz_USB/FS3** 48MHz_DOT AVDD48 GND 3V66_1/VCH_CLK/FS4** PCI_STOP#* 3V66_0 VDD GND SCLK SDATA
1
56-Pin 300-mil SSOP & 240-mil TSSOP
1. These outputs have 2X drive strength. * Internal Pull-up resistor of 120K to VDD ** these inputs have 120K internal pull-down to GND
Block Diagram
PLL2 48MHz_USB 48MHz_DOT X1 X2 XTAL OSC 3V66_1/VCH_CLK REF PLL1 Spread Spectrum WDEN PD# CPU_STOP# PCI_STOP# MULTSEL0 FS (4:0) SDATA SCLK Vtt_PWRGD#
CPU DIVDER Stop
3 3
Frequency Table
FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK MHz 66.66* 100.00 200.00 133.33 100.90 105.00 109.00 114.00 117.00 127.00 130.00 132.50 205.00 170.00 180.00 190.00 3V66 MHz 66.66 66.66 66.66 66.66 67.27 70.00 72.67 76.00 78.00 72.86 74.29 75.71 70.00 56.67 60.00 63.33 PCICLK MHz 33.33 33.33 33.33 33.33 33.63 35.00 36.33 38.00 39.00 36.43 37.14 37.89 35.00 28.33 30.00 31.67
CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (6:0) PCICLK_F (2:0)
PCI DIVDER
Stop
7 3
Control Logic
3V66 DIVDER
5
3V66 (5:2, 0) I REF
Config. Reg.
For additional frequency selections please refer to Byte 0. * For 950211BF version, this frequency is 166.66MHz.
Power Groups
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VDDA = Analog Core PLL VDDREF = REF, Xtal AVDD48 = 48MHz
ICS950211
Integrated Circuit Systems, Inc.
ICS950211
General Description
The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950211 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER 1, 8, 14, 19, 32, 46, 50 2 3 4, 9, 15, 20, 27, 31, 36, 41, 47 24, 23, 22, 21, 33 7,6,5 10 VDD X1 X2 GND 3V66 (5:2, 0) PCICLK_F(2:0) WDEN PCICLK0 PIN NAME TYPE PWR IN OUT PWR OUT OUT IN OUT OUT IN PWR IN IN I/O IN OUT IN PWR OUT IN OUT OUT IN OUT OUT IN IN OUT 3.3V power supply. Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2. Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF). Ground pins for 3.3V supply. 3.3V Fixed 66MHz clock outputs for HUB. 3.3V PCI clock output Hardware enable of watch dog circuit. Enabled when latched high. 3.3V PCI clock output. 3.3V PCI clock outputs. Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. Analog power 3.3V. This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0) inputs are valid and are ready to be sampled (active low). Clock pin for I2C circuitr y 5V tolerant. Data pin for I2C circuitr y 5V tolerant. Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running. 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC). L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . Analog power 3.3V. 3.3V Fixed 48MHz clock output for DOT. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V Fixed 48MHz clock output for USB. This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selecting the current multiplier for CPU outputs "Complementor y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . Halts CPUCLK clocks at logic 0 level, when input low except CPUCLK_F which are free running. 3.3V, 14.318MHz reference clock output. DESCRIPTION
18, 17, 16, 13, 12, 11 PCICLK (6:1) 25 26 28 30 29 34 35 37 38 39 42 43 44, 48, 51 45, 49, 52 40, 55, 54 53 56 PD# VDDA Vtt_PWRGD# SCLK SDATA PCI_STOP# 3V66_1/VCH_CLK FS4 AVDD48 48MHz_DOT FS3 48MHz_USB I REF MULTSEL0 CPUCLKC (2:0) CPUCLKT (2:0) FS (2:0) CPU_STOP# REF
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ICS950211
Maximum Allowed Current
Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
Condition Powerdown Mode (PWRDWN# = 0) Full Active
Host Swing Select Functions
MULTISEL0 Board Target Trace/Term Z 50 ohms 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4* I REF Ioh = 6* I REF Voh @ Z
0 1
1.0V @ 50 0.7V @ 50
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ICS950211
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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ICS950211
Byte 0: Functionality and frequency select register (Default=0)
Bit Description Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK MHz FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0101013V66 MHz PCICLK MHz Spread % PWD
Bit (2,7:4)
Bit 3 Bit 1 Bit 0
0 0 0 0 66.662 66.66 33.33 0 to -0.5% down spread 0 0 0 1 100.00 66.66 33.33 0 to -0.5% down spread 0 0 1 0 200.00 66.66 33.33 0 to -0.5% down spread 33.33 0 to -0.5% down spread 0 0 1 1 133.33 66.66 0 1 0 0 100.90 67.27 33.63 +/-0.35% center spread 0 1 0 1 105.00 70.00 35.00 +/-0.35% center spread +/-0.35% center spread 0 1 1 0 109.00 72.67 36.33 0 1 1 1 114.00 76.00 38.00 +/-0.35% center spread 1 0 0 0 117.00 78.00 39.00 +/-0.35% center spread +/-0.35% center spread 1 0 0 1 127.00 72.86 36.43 1 0 1 0 130.00 74.29 37.14 +/-0.35% center spread 1 0 1 1 132.50 75.71 37.89 +/-0.35% center spread +/-0.35% center spread 1 1 0 0 205.00 70.00 35.00 1 1 0 1 170.00 56.67 28.33 +/-0.35% center spread 1 1 1 0 180.00 60.00 30.00 +/-0.35% center spread +/-0.35% center spread 1 1 1 1 190.00 63.33 31.67 0 0 0 0 133.90 66.95 33.48 +/-0.35% center spread 0 0 0 1 133.33 66.67 33.33 +/-0.35% center spread +/-0.35% center spread 0 0 1 0 120.00 60.00 30.00 0 0 1 1 125.00 62.50 31.25 +/-0.35% center spread 0 1 0 0 134.90 67.45 33.73 +/-0.35% center spread +/-0.35% center spread 0 1 0 1 137.00 68.50 34.25 0 1 1 0 139.00 69.50 34.75 +/-0.35% center spread 0 1 1 1 141.00 70.50 35.25 +/-0.35% center spread +/-0.35% center spread 1 0 0 0 143.00 71.50 35.75 1 0 0 1 145.00 72.50 36.25 +/-0.35% center spread 1 0 1 0 150.00 75.00 37.50 +/-0.35% center spread +/-0.35% center spread 1 0 1 1 155.00 77.50 38.75 1 1 0 0 160.00 80.00 40.00 +/-0.35% center spread 1 1 0 1 150.00 64.29 32.14 +/-0.35% center spread 1 1 1 0 160.00 68.57 34.29 +/-0.35% center spread 1 1 1 1 170.00 72.86 36.43 +/-0.35% center spread Frequency is selected by hardware select, latched inputs Frequency is selected by Bit 2,7:4 Normal Spread spectrum enable Watch dog safe frequency will be selected by latch inputs Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Note 1
0 1 0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 2. For 950211BF version, this frequency is 166.66MHz.
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ICS950211
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 44, 45 48, 49 51, 52 -
PWD 1 1 1 X X X X X
Description CPUT/C2 CPUT/C1 CPUT/C0 FS4 Read FS3 Read FS2 Read FS1 Read FS0 Read
b a ck b a ck b a ck b a ck b a ck
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 18 17 16 13 12 11 10
PWD X 1 1 1 1 1 1 1
Description MULTSEL (Read back) PCICLK_6 PCICLK_5 PCICLK_4 PCICLK_3 PCICLK_2 PCICLK_1 PCICLK_0
Byte 3: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 38 39 35 7 6 5
PWD 1 1 1 0 0 1 1 1
Description 48MHZ_DOT 48MHz_USB Reset gear shift detect 1 = Enable, 0 = Disable Async freq. control bit 0 (See Async Freq. Control Table) 3V66_1/VCH_CLK, (default) = 66.66MHz, 1=48MHz PCICLK_F2 PCICLK_F1 PCICLK_F0
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 33 35 24 23 22 21
PWD 1 X 1 1 1 1 1 1
Description Async. freq. control bit 1 (See Async. Freq. Control Table) Reserved 3V66_0 3V66_1/VCH_CLK 3V66_5 3V66_4 3V66_3 3V66_2
Notes: 1. PWD = Power on Default 2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
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ICS950211
Asynchronous Frequency Control Table
Byte 4 Bit 7 0 0 1 1
Byte 3 Bit 4 0 1 0 1
3V66 [0:3] 66.01 MHz 75.44 MHz 66.66 MHz 88.01 MHz
PCI_F [1:2] PCICK [0:6] 33.005 MHz 37.72 MHz 33.33 MHz 44.005 MHz
Note From Fix PLL (no spread) From Fix PLL (no spread) From main PLL (Default) From Fix PLL (no spread)
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Pin# PWD Description Bi t 7 X 1 CPUCLK T/C0 Free Running Control, 0=Free Running; 1=Stoppable* Bi t 6 X 1 CPUCLK T/C1 Free Running Control, 0=Free Running; 1=Stoppable* Bi t 5 X 1 CPUCLK T/C2 Free Running Control, 0=Free Running; 1=Stoppable* (Reserved) Bi t 4 X 1 Bi t 3 X 1 (Reserved) Bi t 2 X 1 (Reserved) Bi t 1 X 1 (Reserved) Bi t 0 X 1 (Reserved) * This functionality is only available in BF version.
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0
PWD X X X X 0 0 0 1
Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
Byte 7: Revision ID and Device ID Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0 PWD Description 0 0 0 Device ID values will be based on individual device 0 "01H" in this case. 0 0 0 1
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ICS950211
Byte 8: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure byte count and how 0 many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X * 0 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 1 8 * 290ms = 2.3 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Program Enable WD Enable WD Alarm SF4 SF3 SF2 SF1 SF0 PWD 0 0 0 0 0 0 0 0 Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
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Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
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ICS950211
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD Description X X X The Spread Spectrum (12:0) bit will program the spread X precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread X frequency. Default power on is latched FS divider. X X X
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0
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Name CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD X X X X X X X X
Description CPU2 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPU [1:0] clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
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Integrated Circuit Systems, Inc.
ICS950211
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0 3V66 Div 3 3V66 Div 2 3V66 Div 1 3V66 Div 0
Name 3V66_INV 3V66_INV CPU_INV CPU_INV Reserved Reserved Reserved Reserved
PWD X X X X X X X X
PWD X X X X X X X X
Description 3V66 [3:2] clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. 3V66 [1:0] clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 17: Output Divider Control Register
Description 3V66 [3:2] Phase Inversion bit 3V66 Phase Inversion bit CPUCLK2 Phase Inversion bit CPUCLK [1:0] Phase Inversion bit
3V66 [1:0] clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Table 2
Table 1
Div (3:2) Div (1:0) 00 01 10 11 00 /2 /3 /5 /7 01 /4 /6 /10 /14 10 /8 /12 /20 /28 11 /16 /24 /40 /56
Div (3:2) Div (1:0) 00 01 10 11
00 /4 /3 /5 /7
01 /8 /6 /10 /14
10 /16 /12 /20 /28
11 /32 /24 /40 /56
Byte 18: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name CPU_Skew 1 CPU_Skew 0 Reserved Reserved CPU_Skew 1 CPU_Skew 0 Reserved Reserved PWD 0 1 0 0 0 1 0 0 Description These 2 bits delay the CPUCLKC/T2 with respect to CPUCLKC/T (1:0) 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Reserved Reserved These 2 bits delay the CPUCLKC/T (1:0) clock with respect to CPUCLKC/T2 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps Reserved Reserved
Byte 19: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
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Name These 4bits control CPU-3V66(3:1)
PWD 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1
Programming Sequence 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps Reserved Reserved Reserved Reserved Reserved Reserved
These 4 bits control CPU-3V66_0
1 1 1 1 900ps Reserved Reserved Reserved
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ICS950211
Byte 20: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name These 4bits control CPU-PCI(6:0)
PWD 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1
Programming Sequence 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps Reserved Reserved Reserved Reserved Reserved Reserved
These 4 bits control CPU-PCIF(1:0)
1 1 1 1 900ps Reserved Reserved Reserved
Byte 21: Slew Rate Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCIF Slew 1 PCIF Slew 0 PCIF Slew 1 PCIF Slew 0 3V66 (3:2)_Slew 1 3V66 (3:2)_Slew 1 3V66 (1:0)_Slew 1 3V66 (1:0)_Slew 0 PWD 1 0 1 0 1 0 1 0 Description PCIF2(1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCIF1(1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCIF(1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66 (3:2) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66 (1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name REF Slew 1 REF Slew 0 PCI (6:4) Slew 1 PCI (6:4) Slew 0 PCI (3:1) Slew 1 PCI (3:1) Slew 0 PCI0 Slew 1 PCI0 Slew 0 PWD 1 0 1 0 1 0 1 0 Description REF clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (6:4) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (3:1) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI0 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Reserved Reserved VCH Slew 1 VCH Slew 0 48USB Slew 1 48USB Slew 0 48DOT Slew 1 48DOT Slew 0
PWD X X 1 0 1 0 1 0
Description Reserved VCH clock slew rate control bits. 01 = strong: 11 = normal; 10 = weakk 48USB clock slew rate control bits. 01 = strong: 11 = normal; 10 = weakk 48DOT clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
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ICS950211
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance Transition Time Settling Time1 Clk Stabilization Delay
1 1 1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH
CONDITIONS
MIN 2 VSS - 0.3 -5 -5 -200
TYP
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA mA mA mA mA MHz nH pF pF pF mS mS mS nS nS
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors C L = 0 pF; Select @ 66M C L = Full load IREF=2.32 IREF= 5mA VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
100 360 25 45 14.318 7 5 6 45 3 3 1 1 3 10 10
27
36
Guaranteed by design, not 100% tested in production.
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Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; (unless otherwise stated) PARAMETER Current Source Output Impedance Output High Voltage Output High Current Rise Time 1 Differential Crossover Voltage1 Duty Cycle1 Skew , CPU to CPU Jitter, Cycle-to-cycle1
1
SYMBOL ZO VOH IOH tr VX dt tsk tjcyc-cyc VO = VX
CONDITIONS
MIN 3000
TYP
MAX
UNITS
VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF VOL = 20%, VOH = 80% Note 3 VT = 50% VT = 50% VT = VX 175 45 45
0.71 -13.92
1.2 700
V mA ps % % ps ps
50 49.4 40 90
55 55 100 150
Notes: 1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL F0 RDSN11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 d t11 1 tsk1 tjcyc-cyc
1 1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.33
MAX 55 0.55 -33 38
UNITS MHz V V mA mA ns ns % ps ps
1.52 1.45 51.5 155 123
2 2 55 500 250
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS950211
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 R DSP11 VOH1 VOL1 IOH1 IOL1 tr11
1 tf1 1 d t1 tsk11
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.66
MAX 55 0.4 -33 38
UNITS MHz V V mA mA ns ns % ps ps
3 1.3 52 155 150
2 2 55 500 250
tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT to 48 USB Skew Duty Cycle Jitter
1
SYMBOL FO1 RDSN11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 tr
1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V
MIN 12 2.4 -29 29 0.5 0.5 1 1
TYP 48
MAX 55 0.55 -23 27
UNITS MHz V V mA mA ns ns ns ns ns % ps
0.6 0.7 1.1 1.2
1 1 2 2 1
tf1 tskew d t1
1 1
VT=1.5V VT = 1.5 V VT = 1.5 V 45 50.1 130
55 350
1 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS950211
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr1
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP
MAX 60 0.4 -23 27 4 4
UNITS MHz V V mA mA ns ns % ps
tf11 d t11 tjcyc-cyc
53
55 500
Guaranteed by design, not 100% tested in production.
0465E--05/17/05
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Integrated Circuit Systems, Inc.
ICS950211
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Integrated Circuit Systems, Inc.
ICS950211
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 PCICLK_F and PCICLK Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP 3V66 PCI 3V66 to PCI
1
SYMBOL 3V66 PCI S3V66-PCI
CONDITIONS 3V66 pin to pin skew PCI_F and PCI pin to pin skew 3V66 leads 33MHz PCI
MIN 0 0 1.5
TYP 155 302 1.7
MAX UNITS 500 ps 500 ps 3.5 ns
Guaranteed by design, not 100% tested in production.
PD# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
3V66 66MHz Low
66MHz_OUT 66MHz_IN Low
PCICLK_F PCICLK 66MHz_IN Low
PCICLK 66MHz_IN Low
USB/DOT 48MHz 48MHz Low
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Integrated Circuit Systems, Inc.
ICS950211
PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
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Integrated Circuit Systems, Inc.
ICS950211
N
c
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 D SEE VARIATIONS E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 N SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
VARIATIONS D mm. MIN MAX 18.31 18.55
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950211yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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Integrated Circuit Systems, Inc.
ICS950211
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
D mm. MIN 13.90 MAX 14.10 MIN .547
D (inch) MAX .555
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
240 mil TSSOP Package
Ordering Information
ICS950211yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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Integrated Circuit Systems, Inc.
ICS950211
Revision History
Rev. E Issue Date Description 1. Updated Description on Byte 13. 5/17/2005 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant". Page # 9,19-20
0465E--05/17/05
21

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